Philips S1D13505 用户手册
Page 54
Epson Research and Development
Vancouver Design Center
S1D13505
Hardware Functional Specification
X23A-A-001-14
Issue Date: 01/02/02
7.1.7 MIPS/ISA Interface Timing
Figure 7-7: MIPS/ISA Timing
Note
The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is
selected.
selected.
LatchA20
MEMR#
SD[15:0](write)
M/R#, SBHE#
IOCHRDY
BUSCLK
t1
t2
t3
t4
t9
CS#
t7
t8
MEMW#
t11
SD[15:0](read)
t5
t6
t10
t12
t13
SA[19:0]