Philips S1D13505 用户手册
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Epson Research and Development
Vancouver Design Center
S1D13505
Hardware Functional Specification
X23A-A-001-14
Issue Date: 01/02/02
7.3.2 EDO-DRAM CAS Before RAS Refresh Timing
Figure 7-16: EDO-DRAM CAS Before RAS Refresh Timing
Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing
Symbol
Parameter
Min Max
Units
t1
Internal memory clock period
25
ns
t2
RAS# precharge time (REG[22h] bits 3-2 = 00)
2t1 - 3
ns
RAS# precharge time (REG[22h] bits 3-2 = 01)
1.45t1 - 3
ns
RAS# precharge time (REG[22h] bits 3-2 = 10)
1t1 - 3
ns
t3
RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2
= 00)
= 00)
3 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2
= 01)
= 01)
3.45 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2
= 10)
= 10)
4 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2
= 00)
= 00)
2 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2
= 01)
= 01)
2.45 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2
= 10)
= 10)
3 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2
= 00)
= 00)
1 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2
= 01)
= 01)
1.45 t1 - 3
ns
RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2
= 10)
= 10)
2 t1 - 3
ns
t4
CAS# pulse width
t2
ns
t5
CAS# setup time (REG[22h] bits 3-2 = 00 or 10)
0.45 t1 - 3
ns
CAS# setup time (REG[22h] bits 3-2 = 01)
1 t1 - 3
ns
RAS#
CAS#
t2
t3
t1
Memory
Clock
t4
t5
t6