Motorola MVME166D2 用户手册
Functional Description
MVME166IG/D2
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The DRAM map decoder can be programmed to accommodate different base
address(es) and sizes of mezzanine boards. The onboard DRAM is disabled
by a local bus reset and must be programmed before the DRAM can be
accessed. Refer to the MCECC in the MVME166/MVME167/MVME187 Single
Board Computers Programmer’s Reference Guide for detailed programming
information. Most DRAM devices require some number of access cycles
before the DRAMs are fully operational. Normally this requirement is met by
the onboard refresh circuitry and normal DRAM installation. However,
software should insure a minimum of 10 initialization cycles are performed to
each bank of RAM.
address(es) and sizes of mezzanine boards. The onboard DRAM is disabled
by a local bus reset and must be programmed before the DRAM can be
accessed. Refer to the MCECC in the MVME166/MVME167/MVME187 Single
Board Computers Programmer’s Reference Guide for detailed programming
information. Most DRAM devices require some number of access cycles
before the DRAMs are fully operational. Normally this requirement is met by
the onboard refresh circuitry and normal DRAM installation. However,
software should insure a minimum of 10 initialization cycles are performed to
each bank of RAM.
Battery Backed Up RAM and Clock
The MK48T08 RAM and clock chip is used on the MVME166. This chip
provides a time of day clock, oscillator, crystal, power fail detection, memory
write protection, 8KB of RAM, and a battery in one 28-pin package. The clock
provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour
format. Corrections for 28-, 29- (leap year), and 30-day months are
automatically made. No interrupts are generated by the clock. The MK48T08
is an 8 bit device; however, the interface provided by the PCCchip2 supports
8-, 16-, and 32-bit accesses to the MK48T08. Refer to the MK48T08 data sheet
for detailed programming information.
provides a time of day clock, oscillator, crystal, power fail detection, memory
write protection, 8KB of RAM, and a battery in one 28-pin package. The clock
provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour
format. Corrections for 28-, 29- (leap year), and 30-day months are
automatically made. No interrupts are generated by the clock. The MK48T08
is an 8 bit device; however, the interface provided by the PCCchip2 supports
8-, 16-, and 32-bit accesses to the MK48T08. Refer to the MK48T08 data sheet
for detailed programming information.
VMEbus Interface
The local bus to VMEbus interface, the VMEbus to local bus interface, and the
local-VMEbus DMA controller functions on the MVME166 are provided by
the VMEchip2. The VMEchip2 can also provide the VMEbus system controller
functions.
local-VMEbus DMA controller functions on the MVME166 are provided by
the VMEchip2. The VMEchip2 can also provide the VMEbus system controller
functions.
VME Subsystem Bus (VSB) Interface
The local bus to VSB interface and the VSB to local bus interface are provided
by the VSBchip2, only on the MVME166 board. The VSB uses the P2 connector
of the MVME166.
by the VSBchip2, only on the MVME166 board. The VSB uses the P2 connector
of the MVME166.
I/O Interfaces
The MVME166 provides onboard I/O for many system applications. The I/O
functions include serial ports, printer port, Ethernet transceiver interface, and
SCSI mass storage interface.
functions include serial ports, printer port, Ethernet transceiver interface, and
SCSI mass storage interface.
Serial Port Interface
The CD2401 serial controller chip (SCC) is used to implement the four serial
ports. The serial ports support the standard baud rates (110 to 38.4K baud).
The four serial ports on the MVME166 are functionally the same. All serial
ports are full function asynchronous or synchronous ports. They can operate
ports. The serial ports support the standard baud rates (110 to 38.4K baud).
The four serial ports on the MVME166 are functionally the same. All serial
ports are full function asynchronous or synchronous ports. They can operate