Motorola ATCA-717 用户手册

S Hub interface ECC and parity errors

S PCI bus parity errors

The Real−Time Clock (RTC) resides inside the South Bridge and is sourced by an external
32.768 crystal providing a frequency tolerance of 20 ppm. The RTC provides 242 bytes
backed−up CMOS RAM and is fully compliant to:

aa

S DS1287

S MC14618

S Y2K

S PC87911

The Southbridge incorporates a two−stage watchdog timer. For details refer to the Intel
6300ESB I/O controller documentation. On expiry, the watchdog is able to issue a blade
reset.

a

The PCI−X interface is 64−bit wide and runs at 66 MHz. It is compliant to the PCI−X 1.0
specification. On the board 3.3V signalling level is used and an 82546EB/GB dual
Ethernet controller is connected to the PCI−X interface.

a

The South Bridge provides two separate parallel Advanced Technology Attachment
(ATA) interfaces: one primary and one secondary parallel ATA interface. Both interfaces
support all Programmed I/O (PIO) modes as well as all Direct Memory Access (DMA)
modes up to Ultra ATA/100. The combined parallel and serial ATA interface traffic is
indicated by a face plate LED.

a

The primary parallel ATA interface is connected to an on−board 2.5" hard disk which can
be mounted on the blade. The hard disk operates as IDE master.

a