Motorola ATCA-717 用户手册
FPGA Registers
Maps and Registers
PENT/ATCA−717
139
Address Offset
Register
02
16
Lower data register
03
16
Upper data register
04
16
Clock divider register
05
16
I2C Control and Status Register
Command and Status Register
This register controls the transfer of configuration data to and from the Ethernet switch.
a
Table 22:
Command and Status Register
Bit
Description
Access
4..0
PHY internal register address
r/w
5
Command flag
0: Perform write access
1: Perform read access
0: Perform write access
1: Perform read access
r/w
6
Read Error Flag
0: PHY responds to read access
1: Error occurred
0: PHY responds to read access
1: Error occurred
r/wc
7
Interface Status
0: Ready
1: Busy (wait until ready is indicated
before initiating new access)
0: Ready
1: Busy (wait until ready is indicated
before initiating new access)
r
Data Registers
These registers contain the data that is read from or sent to the Ethernet switch.
Clock Divider Register
This register allows to program the frequency of the Ethernet Switch Management clock.
a
I2C Control and Status Register
The Ethernet switch obtains its configuration data from a PROM device that is connected
to it. This register allows to access this PROM and is used for PROM updates.
to it. This register allows to access this PROM and is used for PROM updates.
a
Reset Registers
The blade provides two registers which are related to blade resets:
aaaaa
S Reset source register (index address 0x00)