Motorola ATCA-717 用户手册
Maps and Registers
FPGA Registers
148
PENT/ATCA−717
Table 35:
Version Register
Bit
Description
Default
Access
7..0
FPGA version
FD
16
a
(at the time of
writing this guide)
r
Access Control Register
This register determines the current owner of the following interfaces:
S Clock synchronisation building block interface
S Ethernet switch management interface
S SPROM update interface
The current owner of each interface is either the IPMC or the host CPU.
The current owner of each interface is either the IPMC or the host CPU.
a
Only the current owner has write access to the corresponding registers. The
non−proprietor has only read access.
non−proprietor has only read access.
a
If the non−proprietor wants to become owner, it has to request ownership from the
current owner. The current owner then has to grant ownership by inverting the bit
corresponding to the interface.
current owner. The current owner then has to grant ownership by inverting the bit
corresponding to the interface.
a
Table 36:
Access Control Register
Bit
Description
Default
Access
0
Indicates the current owner of the clock
synchronisation building block interface
0: Host
synchronisation building block interface
0: Host
a
1: IPMC
0
2
r/w
1
Indicates current owner of Ethernet switch
management interface
0: Host
1: IPMC
management interface
0: Host
1: IPMC
1
2
r/w
2
Indicates the current owner of the SPROM
update interface
0: Host
1: IPMC
update interface
0: Host
1: IPMC
0
2
r/w
7..3
Reserved
00000
2
r