Motorola MVME166IG 用户手册

Board Level Hardware Description

1-18

There are two points of view for memory maps: 1) the mapping of all resources 
as viewed by local bus masters (local bus memory map), 2) the mapping of 
onboard resources as viewed by externa masters (VMEbus memory map or 
VSB memory map).  

The local bus memory map is split into different address spaces by the transfer 
type (TT) signals.  The local resources respond to the normal access and 
interrupt acknowledge codes.  

The memory map of devices that respond to the normal address range is 
shown in the following tables.  The normal address range is defined by the 
Transfer Type (TT) signals on the local bus.  On the MVME166, Transfer Types 
0, 1, and 2 define the normal address range.  

Table 1-2 is the entire map from $00000000 to $FFFFFFFF.  Many areas of the 
map are user-programmable, and suggested uses are shown in the table.  The 
cache inhibit function is programmable in the MMUs.  The onboard I/O space 
must be marked cache inhibit and serialized in its page table.  

Table 1-3 further defines the map for the local I/O devices.