National Instruments 3.21E+04 用户手册
Chapter 4 Signal Connections
AT-MIO/AI E Series User Manual
4-52
National Instruments Corporation
The GATE and OUT signal transitions shown in Figure 4-37 are
referenced to the rising edge of the SOURCE signal. This timing
diagram assumes that the counters are programmed to count rising
edges. The same timing diagram, but with the source signal inverted
and referenced to the falling edge of the source signal, would apply
when the counter is programmed to count falling edges.
referenced to the rising edge of the SOURCE signal. This timing
diagram assumes that the counters are programmed to count rising
edges. The same timing diagram, but with the source signal inverted
and referenced to the falling edge of the source signal, would apply
when the counter is programmed to count falling edges.
The GATE input timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on your
AT E Series board. Figure 4-37 shows the GATE signal referenced to
the rising edge of a source signal. The gate must be valid (either high
or low) for at least 10 ns before the rising or falling edge of a source
signal for the gate to take effect at that source edge, as shown by t
SOURCE input or to one of the internally generated signals on your
AT E Series board. Figure 4-37 shows the GATE signal referenced to
the rising edge of a source signal. The gate must be valid (either high
or low) for at least 10 ns before the rising or falling edge of a source
signal for the gate to take effect at that source edge, as shown by t
gsu
and t
gh
in Figure 4-37. The gate signal is not required to be held after
the active edge of the source signal.
If an internal timebase clock is used, the gate signal cannot be
synchronized with the clock. In this case, gates applied close to a
source edge take effect either on that source edge or on the next one.
This arrangement results in an uncertainty of one source clock period
with respect to unsynchronized gating sources.
synchronized with the clock. In this case, gates applied close to a
source edge take effect either on that source edge or on the next one.
This arrangement results in an uncertainty of one source clock period
with respect to unsynchronized gating sources.
The OUT output timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated clock signals on the
AT E Series boards. Figure 4-37 shows the OUT signal referenced to
the rising edge of a source signal. Any OUT signal state changes occur
within 80 ns after the rising or falling edge of the source signal.
SOURCE input or to one of the internally generated clock signals on the
AT E Series boards. Figure 4-37 shows the OUT signal referenced to
the rising edge of a source signal. Any OUT signal state changes occur
within 80 ns after the rising or falling edge of the source signal.
FREQ_OUT Signal
This signal is available only as an output on the FREQ_OUT pin. The
FREQ_OUT signal is the output of the AT E Series board frequency
generator. The frequency generator is a 4-bit counter that can divide its
input clock by the numbers 1 through 16. The input clock of the
frequency generator is software selectable from the internal
10 MHz and 100 kHz timebases. The output polarity is software
selectable. This output is set to tri-state at startup.
FREQ_OUT signal is the output of the AT E Series board frequency
generator. The frequency generator is a 4-bit counter that can divide its
input clock by the numbers 1 through 16. The input clock of the
frequency generator is software selectable from the internal
10 MHz and 100 kHz timebases. The output polarity is software
selectable. This output is set to tri-state at startup.