Soyo SY-K7VTA Pro 用户手册
BIOS Setup Utility
SY-K7VTA PRO
65
After you have completed the changes, press [Esc] and follow the
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.
instructions on your screen to save your settings or exit without saving.
The following table describes each field in the Advanced Chipset Features
Menu and how to configure each parameter.
3-4.1 CHIPSET FEATURES SETUP
CHIPSET
FEATURES
FEATURES
Setting
Description
Note
Disabled
DRAM
Timing By
SPD
Timing By
SPD
Enabled
If enable the DRAM will auto
detect the DRAM timing
detect the DRAM timing
Default
100MHz
Default
DRAM Clock
133MHz
This item allows you to control the
DRAM speed.
DRAM speed.
SDRAM Cycle
Length
Length
3
2
2
When synchronous DRAM is
installed, the number of clock
cycles of CAS latency depends on
the DRAM timing. Do not reset
this field from the default value
specified by the system designer.
installed, the number of clock
cycles of CAS latency depends on
the DRAM timing. Do not reset
this field from the default value
specified by the system designer.
Default
Disabled
Default
Bank
Interleave
Interleave
2 Bank
4 Bank
4 Bank
Increase DRAM performance.
Disabled
Default
Memory Hole
Enabled
Some interface cards will map
their ROM address to this area. If
this occurs, select [Enabled] in this
field.
their ROM address to this area. If
this occurs, select [Enabled] in this
field.
Disabled
PCI master
Pipeline Req Enabled
Pipeline Req Enabled
Disabled/Enabled PCI Master
Pipeline Req.
Pipeline Req.
Default
Disabled
P2C/C2P
Concurrency
Concurrency
Enabled
This item allows you to
enable/disable the PCI to CPU,
CPU to PCI concurrency.
enable/disable the PCI to CPU,
CPU to PCI concurrency.
Default