Cypress CY7C1516JV18 用户手册
CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
CY7C1518JV18, CY7C1520JV18
Document Number: 001-12559 Rev. *D
Page 3 of 26
Logic Block Diagram (CY7C1518JV18)
Logic Block Diagram (CY7C1520JV18)
Write
Reg
Reg
Write
Reg
Reg
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add
. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
18
BWS
[1:0]
V
REF
W
rite Add. Decode
18
22
C
C
18
LD
Control
Burst
Logic
Logic
A0
A
(21:1)
R/W
DOFF
2M x
18 Array
2M x 18 Arr
a
y
21
18
DQ
[17:0]
18
CQ
CQ
Write
Reg
Reg
Write
Reg
Reg
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read
A
d
d. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
36
BWS
[3:0]
V
REF
W
rite Add. Decode
36
21
C
C
36
LD
Control
Burst
Logic
Logic
A0
A
(20:1)
R/W
DOFF
1M x
36 Array
1M x 36 Arr
a
y
20
36
DQ
[35:0]
36
CQ
CQ