Cypress CY7C1518KV18 用户手册

Document Number: 001-00437 Rev. *E

Page 7 of 30

CQ

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock 

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing 

for the echo clocks is shown in the AC Timing table.

CQ

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock 

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing 

for the echo clocks is shown in the AC Timing table.

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus 

impedance. CQ, CQ, and Q

[x:0] 

output impedance are set to 0.2 x RQ, where RQ is a resistor connected 

between ZQ and ground. Alternatively, this pin can be connected directly to V

DDQ

, which enables the 

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

− Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing 

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin 

is connected to a pull up through a 10 K

Ω or less pull up resistor. The device behaves in DDR-I mode 

when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz 

with DDR-I timing. 

TDO

Output

TDO for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

Input

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

Input

Not Connected to the Die. Can be tied to any voltage level.

V

REF

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC 

measurement points.

V

DD

Power Supply Power supply Inputs to the Core of the Device. 

V

SS

Ground

Ground for the Device. 

V

DDQ

Power Supply Power Supply Inputs for the Outputs of the Device.

 (continued)