Cypress CY7C1525JV18 用户手册
CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18
CY7C1512JV18, CY7C1514JV18
Document #: 001-14435 Rev. *C
Page 19 of 26
Power Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
Power Up, when the DOFF is tied HIGH, the DLL gets locked
after 1024 cycles of stable clock.
predefined manner to prevent undefined operations. During
Power Up, when the DOFF is tied HIGH, the DLL gets locked
after 1024 cycles of stable clock.
Power Up Sequence
■
Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
HIGH or LOW)
❐
Apply V
DD
before V
DDQ
❐
Apply V
DDQ
before V
REF
or at the same time as V
REF
■
Provide stable power and clock (K, K) for 1024 cycles to lock
the DLL.
the DLL.
DLL Constraints
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
have low phase jitter, which is specified as t
KC Var
.
■
The DLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid DLL locking provide 1024 cycles
stable clock to relock to the desired clock frequency.
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid DLL locking provide 1024 cycles
stable clock to relock to the desired clock frequency.
Power Up Waveforms
> 1024 Stable clock
Start Normal
Operation
DOFF
Stable (< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
K
K
DDQ
DD
V
V
/
DDQ
DD
V
V
/
Clock Start (Clock Starts after Stable)
DDQ
DD
V
V
/
~ ~
~~
Unstable Clock