Cypress CY7C1525JV18 用户手册
CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18
CY7C1512JV18, CY7C1514JV18
Document #: 001-14435 Rev. *C
Page 3 of 26
Logic Block Diagram (CY7C1512JV18)
Logic Block Diagram (CY7C1514JV18)
2M x 18 Arra
y
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add
. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
18
BWS
[1:0]
V
REF
W
rite Add. D
e
co
de
Write
Reg
18
A
(20:0)
21
CQ
CQ
DOFF
Q
[17:0]
18
18
18
Write
Reg
C
C
2M x 18 Arra
y
1M x 36 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read
A
d
d. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
36
BWS
[3:0]
V
REF
W
rite Add.
Decode
Write
Reg
36
A
(19:0)
20
CQ
CQ
DOFF
Q
[35:0]
36
36
36
Write
Reg
C
C
1M x 36 Array