Cypress CY8C24423 用户手册
CY8C24123
CY8C24223, CY8C24423
Document Number: 38-12011 Rev. *G
Page 27 of 43
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C
and -40°C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 25. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
IMO
Internal Main Oscillator Frequency
23.4
24
24.6
a
MHz
Trimmed. Using factory trim
values.
values.
F
CPU1
CPU Frequency (5V Nominal)
0.93
24
24.6
a,b
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
MHz
F
CPU2
CPU Frequency (3.3V Nominal)
0.93
12
12.3
b,c
c.
3.0V < Vdd < 3.6V. See Application Note
“Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for opera-
tion at 3.3V.
MHz
F
48M
Digital PSoC Block Frequency
0
48
49.2
a,b,d
d. See the individual user module data sheets for information on maximum frequencies for user modules.
MHz
Refer to the AC Digital Block
Specifications.
Specifications.
F
24M
Digital PSoC Block Frequency
0
24
24.6
b,e,d
e. 3.0V < 5.25V.
MHz
F
32K1
Internal Low Speed Oscillator Frequency
15
32
64
kHz
F
32K2
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
crystal dependent. 50% duty
cycle.
F
PLL
PLL Frequency
–
23.986
–
MHz
Is a multiple (x732) of crystal
frequency.
frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
–
–
600
ps
T
PLLSLEW
PLL Lock Time
0.5
–
10
ms
T
PLLSLEWSLOW
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
T
OS
External Crystal Oscillator Startup to 1%
–
1700
2620
ms
T
OSACC
External Crystal Oscillator Startup to 100 ppm
–
2800
3800
f
f.
The crystal oscillator frequency is within 100 ppm of its final value by the end of the T
osacc
period. Correct operation assumes a properly loaded 1 uW maximum
drive level 32.768 kHz crystal. 3.0V
≤ Vdd ≤ 5.5V, -40
o
C
≤ T
A
≤ 85
o
C.
ms
Jitter32k
32 kHz Period Jitter
–
100
ns
T
XRST
External Reset Pulse Width
10
–
–
μs
DC24M
24 MHz Duty Cycle
40
50
60
%
Step24M
24 MHz Trim Step Size
–
50
–
kHz
Fout48M
48 MHz Output Frequency
46.8
48.0
49.2
a,c
MHz
Trimmed. Using factory trim
values.
values.
Jitter24M1
24 MHz Period Jitter (IMO)
–
600
ps
F
MAX
Maximum frequency of signal on row input or
row output.
row output.
–
–
12.3
MHz
T
RAMP
Supply Ramp Time
0
–
–
μs