Cypress CY7C1356C 用户手册

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页码 28
 
CY7C1354C
CY7C1356C
Document #: 38-05538 Rev. *G
Page 2 of 28
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ
Sleep
Control
Logic Block Diagram–CY7C1356C (512K x 18)
Selection Guide
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
3.2
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
40
40
40
mA