Cypress CY7C1347G 用户手册

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页码 22
 
CY7C1347G
Document #: 38-05516 Rev. *F
Page 14 of 22
Figure 7.  Read/Write Cycle Timing
Switching Waveforms
  (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A2
tCEH
tCES
BWE,
BW[A:D]
Data Out (Q)
High-Z
ADV
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
Data In (D)
BURST READ
Back-to-Back  READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWEH
tWES
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
tCLZ
tCO
Back-to-Back
WRITEs
A1
DON’T CARE
UNDEFINED
A3
Notes
18. The data bus (Q) remains in High-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
19. GW is HIGH.