Cypress CY8C21634 用户手册
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-12025 Rev. *O
Page 27 of 45
Figure 16. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 17. 32 kHz Period Jitter (ILO) Timing Diagram
Table 26. 2.7V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
IMO12
Internal Main Oscillator Frequency for 12 MHz
11.5
12
0
12.7
MHz
Trimmed for 2.7V operation
using factory trim values.
See
SLIMO mode = 1.
F
IMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35
MHz
Trimmed for 2.7V operation
using factory trim values.
See
SLIMO mode = 1.
F
CPU1
CPU Frequency (2.7V Nominal)
0.093
3
3.15
MHz
24 MHz only for SLIMO
mode = 0.
F
BLK27
Digital PSoC Block Frequency (2.7V Nominal)
0
12
12.5
MHz
Refer to the AC Digital Block
Specifications.
F
32K1
Internal Low Speed Oscillator Frequency
8
32
96
kHz
Jitter32k
32 kHz RMS Period Jitter
–
150
200
ns
Jitter32k
32 kHz Peak-to-Peak Period Jitter
–
1400
–
T
XRST
External Reset Pulse Width
10
–
–
μs
F
MAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
T
RAMP
Supply Ramp Time
0
–
–
μs
Jitter24M1
F
24M
Jitter32k
F
32K1
Notes
16. 2.4V < Vdd < 3.0V.
17. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
18. See Application Note
17. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
18. See Application Note
“Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.