Cypress CY8C21634 用户手册
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-12025 Rev. *O
Page 34 of 45
Packaging Information
This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
.
Packaging Dimensions
Figure 20. 16-Pin (150-Mil) SOIC
Figure 21. 20-Pin (210-MIL) SSOP
PIN 1 ID
0°~8°
1
8
9
16
SEATING PLANE
0.230[5.842]
0.244[6.197]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.386[9.804]
0.393[9.982]
0.393[9.982]
0.050[1.270]
BSC
BSC
0.061[1.549]
0.068[1.727]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0098[0.249]
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.016[0.406]
0.010[0.254] X 45°
0.004[0.102]
REFERENCE JEDEC MS-012
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
PACKAGE WEIGHT 0.15gms
51-85068 *B
51-85077 *C