Cypress CY7C1007B 用户手册
1M x 1 Static RAM
CY7C107B
CY7C1007B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05030 Rev. **
Revised September 7, 2001
07B
Features
• High speed
— t
AA
= 12 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(D
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(D
IN
) is written into the memory location specified on the ad-
dress pins (A
0
through A
19
).
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (D
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (D
OUT
)
pin.
The output pin (D
OUT
) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
operation (CE and WE LOW).
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
the CY7C1007B is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
Top View
SOJ
512x2048
ARRAY
A
5
A
6
A
7
COLUMN
DECODER
ROW
DE
CODE
R
S
E
N
S
E AM
PS
POWER
DOWN
WE
CE
INPUT BUFFER
D
OUT
D
IN
A
4
A
3
A
2
A
1
A
0
1
2
3
4
3
4
5
6
6
7
8
9
10
11
8
9
10
11
14
15
16
20
19
18
17
19
18
17
21
24
23
22
22
12
13
13
25
28
27
26
26
GND
A
11
A
12
A
13
A
14
WE
V
CC
A
9
A
10
CE
A
0
D
OUT
D
IN
A
8
A
7
A
6
A
2
A
1
A
4
NC
NC
A
15
A
16
A
8
A
12
A
14
A
16
A
15
A
10
A
11
A
13
A
17
A
18
A
19
A
17
A
18
A
19
A
5
A
3
A
9
107B-1
107B-2
Selection Guide
7C107B-12
7C1007B-12
7C107B-15
7C1007B-15
7C107B-20
7C1007B-20
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
Maximum Access Time (ns)
12
15
20
25
35
Maximum Operating
Current (mA)
Current (mA)
90
80
75
70
60
Maximum CMOS Standby
Current SB2 (mA)
Current SB2 (mA)
2
2
2
2
2