Cypress CY7C1177V18 用户手册
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 3 of 27
Logic Block Diagram (CY7C1168V18)
Logic Block Diagram (CY7C1170V18)
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
R
ead Add. Decode
Read Data Reg.
R/W
DQ
[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS
[1:0]
V
REF
W
rite Add. Decode
18
18
LD
Control
19
512
K x 18 Ar
ray
512K x
18 Array
Write
Reg
Reg
Write
Reg
Reg
CQ
CQ
R/W
DOFF
QVLD
18
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. D
e
code
Read Data Reg.
R/W
DQ
[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS
[3:0]
V
REF
W
rite Add. D
e
cod
e
36
36
LD
Control
18
256K
x 36 Arr
a
y
256K x
36 Array
Write
Reg
Reg
Write
Reg
Reg
CQ
CQ
R/W
DOFF
QVLD
36