Cypress CY62148E 用户手册
CY62148E MoBL
®
4-Mbit (512K x 8) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05442 Rev. *F
Revised March 28, 2007
Features
• Very high speed: 45 ns
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62148B
• Ultra low standby power
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62148B
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA (Industrial)
• Ultra low active power
— Typical active current: 2.0 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin TSOP II and 32-pin SOIC
packages
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE HIGH).
The eight input and output pins (IO
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE HIGH).
The eight input and output pins (IO
0
through IO
7
) are placed
in a high impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO
(WE) inputs LOW. Data on the eight IO pins (IO
0
through IO
7
)
is then written into the location specified on the address pins
(A
(A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
Product Portfolio
Product
Range
V
CC
Range (V)
Speed
(ns)
Power Dissipation
Operating I
CC
(mA)
Standby I
SB2
(
µA)
f = 1MHz
f = f
max
Min
Typ
Max
Typ
Max
Typ
Max
Typ
[3]
Max
CY62148ELL TSOP II
Ind’l
4.5
5.0
5.5
45
2
2.5
15
20
1
7
CY62148ELL SOIC
Ind’l/Auto-A
4.5
5.0
5.5
55
2
2.5
15
20
1
7
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at
http://www.cypress.com
.
2. SOIC package is available only in 55 ns speed bin.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.