Cypress CY7C1294DV18 用户手册
CY7C1292DV18
CY7C1294DV18
CY7C1294DV18
Document #: 001-00350 Rev. *A
Page 4 of 23
Pin Definitions
Pin Name
I/O
Pin Description
D
[x:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1292DV18 - D
operations.
CY7C1292DV18 - D
[17:0]
CY7C1294DV18 - D
[35:0]
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted
active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the
Write port will cause D
active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the
Write port will cause D
[x:0]
to be ignored.
BWS
0
, BWS
1
,
BWS
2
, BWS
3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3
− active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1292DV18
portion of the Write operations. Bytes not written remain unaltered.
CY7C1292DV18
− BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
.
CY7C1294DV18
− BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,BWS
2
controls D
[26:18]
and
BWS
3
controls D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write address)
clocks during active Read and Write operations. These address inputs are multiplexed for both
Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of
256K x 18) for CY7C1292DV18 and 256K x 36 (2 arrays each of 128K x 36) for CY7C1294DV18.
Therefore 18 address inputs for CY7C1292DV18 and 17 address inputs for CY7C1294DV18.
These inputs are ignored when the appropriate port is deselected.
clocks during active Read and Write operations. These address inputs are multiplexed for both
Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of
256K x 18) for CY7C1292DV18 and 256K x 36 (2 arrays each of 128K x 36) for CY7C1294DV18.
Therefore 18 address inputs for CY7C1292DV18 and 17 address inputs for CY7C1294DV18.
These inputs are ignored when the appropriate port is deselected.
Q
[x:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K
and K when in single clock mode. When the Read port is deselected, Q
data is driven out on the rising edge of both the C and C clocks during Read operations or K
and K when in single clock mode. When the Read port is deselected, Q
[x:0]
are automatically
tri-stated.
CY7C1292DV18
CY7C1292DV18
− Q
[17:0]
CY7C1294DV18
− Q
[35:0]
RPS
Input-
Synchronous
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected.
When deselected, the pending access is allowed to complete and the output drivers are
automatically tri-stated following the next rising edge of the C clock. Each read access consists
of a burst of two sequential transfers.
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected.
When deselected, the pending access is allowed to complete and the output drivers are
automatically tri-stated following the next rising edge of the C clock. Each read access consists
of a burst of two sequential transfers.
C
Input-Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
C
Input-Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-Clock
Negative Input Clock Input. The rising edge of K is used to capture synchronous inputs being
presented to the device and to drive out data through Q
presented to the device and to drive out data through Q
[x:0]
when in single clock mode.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
V
V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.