Cypress CY7C1380D 用户手册

Document #: 38-05543 Rev. *F

Page 13 of 34

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary ‘01’ pattern to enable fault

isolation of the board-level serial test data path.

Bypass Register
To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between the

TDI and TDO balls. This enables data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW (V

SS

)

when the BYPASS instruction is executed.

Boundary Scan Register
The boundary scan register is connected to all the input and

bidirectional balls on the SRAM. 
The boundary scan register is loaded with the contents of the

RAM input and output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

balls when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can

be used to capture the contents of the input and output ring.
The boundary scan order tables show the order in which the bits

are connected. Each bit corresponds to one of the bumps on the

SRAM package. The MSB of the register is connected to TDI,

and the LSB is connected to TDO.

Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in the 

on page 16.

Overview
Eight different instructions are possible with the three bit

instruction register. All combinations are listed in 

on page 16. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions

are described in detail in this section.
Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO balls. To execute

the instruction once it is shifted in, the TAP controller must be

moved into the Update-IR state.

EXTEST
The EXTEST instruction enables the preloaded data to be driven

out through the system output pins. This instruction also selects

the boundary scan register to be connected for serial access

between the TDI and TDO in the Shift-DR controller state.

IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to

be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and enables

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register

upon power up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to

be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. The SAMPLE Z command places

all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the input and output pins is captured

in the boundary scan register. 
The TAP controller clock can only operate at a frequency up to

20 MHz, while the SRAM clock operates more than an order of

magnitude faster. As there is a large difference in the clock

frequencies, it is possible that during the Capture-DR state, an

input or output undergoes a transition. The TAP may then try to

capture a signal while in transition (metastable state). This does

not harm the device, but there is no guarantee as to the value

that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture setup plus hold

times (t

CS

 and t

CH

). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells prior

to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required; that is, while data captured is

shifted out, the preloaded data is shifted in.

BYPASS
When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO balls. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tri-state mode. 
The boundary scan register has a special bit located at Bit #85

(for 119-BGA package) or Bit #89 (for 165-fBGA package). When

this scan cell, called the “extest output bus tri-state,” is latched

into the preload register during the Update-DR state in the TAP

controller, it directly controls the state of the output (Q-bus) pins,