Cypress CY7C1231H 用户手册
2-Mbit (128K x 18) Flow-Through SRAM
with NoBL™ Architecture
CY7C1231H
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-00207 Rev. *B
Revised April 26, 2006
Features
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 18 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 6.5 ns (133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed write
• Asynchronous Output Enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
[1]
The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
C
MODE
BW
A
BW
B
WE
CE
1
CE
2
CE
3
OE
READ LOGIC
DQs
DQP
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
D0
Q1
Q0
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
A
T
A
S
T
E
E
T
E
E
R
I
N
G
G
S
E
E
N
S
E
E
A
M
P
S
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
U
T
P
P
U
T
B
U
F
F
E
F
E
R
S
E
ZZ
SLEEP
CONTROL
Logic Block Diagram