Cypress CY7C0832BV 用户手册

FLEx18™ 3.3V 64K/128K x 36 and

128K/256K x 18 Synchronous Dual-Port RAM

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198 Champion Court

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San Jose

,

CA 95134-1709

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408-943-2600

Document #: 38-06059 Rev. *S

 Revised March 03, 2009

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True Dual-Ported Memory Cells that Allow Simultaneous 
Access of the Same Memory Location

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Synchronous Pipelined Operation

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Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices

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Pipelined Output Mode Allows Fast Operation

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0.18 micron CMOS for Optimum Speed and Power

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High Speed Clock to Data Access

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3.3V Low Power

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Active as Low as 225 mA (typ)

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Standby as Low as 55 mA (typ)

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Mailbox Function for Message Passing

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Global Master Reset

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Separate Byte Enables on Both Ports

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Commercial and Industrial Temperature Ranges

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IEEE 1149.1 Compatible JTAG Boundary Scan

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144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)

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120 TQFP (14 mm x 14 mm x 1.4 mm)

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Pb-Free Packages Available

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Counter Wrap Around Control

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Internal Mask Register Controls Counter Wrap Around

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Counter-Interrupt Flags to Indicate Wrap Around

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Memory Block Retransmit Operation

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Counter Readback on Address Lines

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Mask Register Readback on Address Lines

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Dual Chip Enables on Both Ports for Easy Depth Expansion

The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location by
more than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal setup and hold
time.

During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times. 

A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.

Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST). 

The CY7C0833AV device in this family has limited features. See

for details.

Part Number

CY7C0837AV

CY7C0830AV

CY7C0831AV

CY7C0832AV

CY7C0832BV 

CY7C0833AV

Maximum Speed (MHz)

167

167

167

167

133

133

Maximum Access Time - 
Clock to Data (ns)

4.0

4.0

4.0

4.0

4.4

4.7

Typical Operating 
Current (mA)

225

225

225

225

225

270

Package

144 FBGA

120 TQFP
144 FBGA

120 TQFP
144 FBGA

120 TQFP
144 FBGA

120 TQFP

 144 FBGA

1. CY7C0832AV and CY7C0832BV are functionally identical.