Cypress CY7C1515JV18 用户手册
CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Document Number: 001-12560 Rev. *C
Page 2 of 27
Logic Block Diagram (CY7C1511JV18)
Logic Block Diagram (CY7C1526JV18)
2M x 8 A
rr
a
y
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add
. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
21
32
8
NWS
[1:0]
V
REF
W
rite Add. D
e
co
de
Write
Reg
16
A
(20:0)
21
8
CQ
CQ
DOFF
Q
[7:0]
8
8
8
8
Write
Reg
Write
Reg
Write
Reg
C
C
2M x 8 A
rr
a
y
2M x 8 A
rr
a
y
2M x 8 A
rr
a
y
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read
A
d
d. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
9
BWS
[0]
V
REF
W
rite Add.
Decode
Write
Reg
18
A
(20:0)
21
9
CQ
CQ
DOFF
Q
[8:0]
9
9
9
9
Write
Reg
Write
Reg
Write
Reg
C
C
2
M
x 9 Arra
y
2
M
x 9 Arra
y
2
M
x 9 Arra
y
2
M
x 9 Arra
y