Cypress CY14B101Q2 用户手册

Document #: 001-50091 Rev. *A

Page 18 of 22

  

t

DHSB 

HSB To Output Active Time when write latch not set

25

ns

t

PHSB

Hardware STORE Pulse Width

15

ns

HSB (IN)

HSB (OUT)

SO

RWI

HSB (IN)

HSB (OUT)

RWI

tHHHD

tSTORE

tPHSB

tDELAY

tLZHSB

tDELAY

tDHSB

tDHSB

tPHSB

HSB pin is driven high to VCC only by Internal 

100K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

Write Latch not set

Write Latch set