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Cypress CY7C2561KV18 用户手册

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页码 共 29
PRELIMINARY
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Document Number: 001-15887 Rev. *E
Page 3 of 29
Logic Block Diagram (CY7C2563KV18)
Logic Block Diagram (CY7C2565KV18)
1M x 18 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add
. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
18
BWS
[1:0]
V
REF
W
rite Add. D
eco
de
Write
Reg
36
A
(19:0)
20
1M x 18 Array
1M x 18 Array
1M x 18 Array
18
CQ
CQ
DOFF
Q
[17:0]
QVLD
18
18
18
Write
Reg
Write
Reg
Write
Reg
18
51
2K x 36
 Arra
y
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read
 A
d
d. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
19
144
36
BWS
[3:0]
V
REF
W
rite Add
. Decode
Write
Reg
72
A
(18:0)
19
51
2K x 36
 Arra
y
51
2K x 36
 Arra
y
51
2K x 36
 Arra
y
36
CQ
CQ
DOFF
Q
[35:0]
QVLD
36
36
36
Write
Reg
Write
Reg
Write
Reg
36