Cypress CY7C141 用户手册
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E
Page 8 of 19
Switching Characteristics
Over the Operating Range
Parameter
Description
7C130-35
7C131-35
7C140-35
7C141-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
7C131-55
7C140-55
7C141-55
Unit
Min
Max
Min
Max
Min
Max
Read Cycle
t
RC
Read Cycle Time
35
45
55
ns
t
AA
Address to Data Valid
35
45
55
ns
t
OHA
Data Hold from Address Change
0
0
0
ns
t
ACE
CE LOW to Data Valid
[13]
35
45
55
ns
t
DOE
OE LOW to Data Valid
20
25
25
ns
t
LZOE
OE LOW to Low Z
3
3
3
ns
t
HZOE
OE HIGH to High Z
20
20
25
ns
t
LZCE
CE LOW to Low Z
5
5
5
ns
t
HZCE
CE HIGH to High Z
20
20
25
ns
t
PU
CE LOW to Power Up
[10]
0
0
0
ns
t
PD
CE HIGH to Power Down
35
35
35
ns
Write Cycle
t
WC
Write Cycle Time
35
45
55
ns
t
SCE
CE LOW to Write End
30
35
40
ns
t
AW
Address Setup to Write End
30
35
40
ns
t
HA
Address Hold from Write End
2
2
2
ns
t
SA
Address Setup to Write Start
0
0
0
ns
t
PWE
R/W Pulse Width
25
30
30
ns
t
SD
Data Setup to Write End
15
20
20
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
HZWE
R/W LOW to High Z
20
20
25
ns
t
LZWE
R/W HIGH to Low Z
0
0
0
ns
Busy/Interrupt Timing
t
BLA
BUSY LOW from Address Match
20
25
30
ns
t
BHA
BUSY HIGH from Address Mismatch
20
25
30
ns
t
BLC
BUSY LOW from CE LOW
20
25
30
ns
t
BHC
BUSY HIGH from CE HIGH
20
25
30
ns
t
PS
Port Set Up for Priority
5
5
5
ns
t
WB
R/W LOW after BUSY LOW
0
0
0
ns
t
WH
R/W HIGH after BUSY HIGH
30
35
35
ns
t
BDD
BUSY HIGH to Valid Data
35
45
45
ns
t
DDD
Write Data Valid to Read Data Valid
ns
t
WDD
Write Pulse to Data Delay
Note 19
Note 19
Note 19
ns
Interrupt Timing
t
WINS
R/W to INTERRUPT Set Time
25
35
45
ns
t
EINS
CE to INTERRUPT Set Time
25
35
45
ns
t
INS
Address to INTERRUPT Set Time
25
35
45
ns
t
OINR
OE to INTERRUPT Reset Time
25
35
45
ns
t
EINR
CE to INTERRUPT Reset Time
25
35
45
ns
t
INR
Address to INTERRUPT Reset Time
[17]
25
35
45
ns