Cypress CY7C1393BV18 用户手册

Document #: 38-05623 Rev. *D

Revised June 2, 2008

Page 31 of 31

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.

© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress. 

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Use may be limited by and subject to the applicable Cypress software license agreement. 

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at 

cypress.com/sales.

PSoC

psoc.cypress.com

Clocks & Buffers

clocks.cypress.com

Wireless

wireless.cypress.com

Memories

memory.cypress.com

Image Sensors

image.cypress.com

General

psoc.cypress.com/solutions

Low Power/Low Voltage

psoc.cypress.com/low-power

            

Precision Analog 

psoc.cypress.com/precision-analog

LCD Drive

psoc.cypress.com/lcd-drive

CAN 2.0b

psoc.cypress.com/can

USB

psoc.cypress.com/usb

*D

2511728

06/03/08

VKN/PYRS Updated Logic Block diagrams

Updated I

DD

/I

SB

 specs

Added footnote# 19 related to I

DD

Updated power up sequence waveform and its description
Changed DLL minimum operating frequency from 80 MHz to 120 MHz
Changed 

Θ

JA 

spec from 28.51 to 18.7

Changed 

Θ

JC 

spec from 5.91 to 4.5

Changed t

CYC

 maximum spec to 8.4 ns for all speed bins

Modified footnotes 21 and 28