Compaq MSEBX900 用户手册
DIGITAL-LOGIC AG
MSEBX800/900 Detailed Manual V1.0
35
5.3. Controllers
5.3.1.
Interrupt Controllers
An 8259A compatible interrupt controller, within the chipset, provides seven prioritized interrupt levels. Of
these, several are normally associated with the board's onboard device interfaces and controllers, and
several are available on the AT expansion bus.
these, several are normally associated with the board's onboard device interfaces and controllers, and
several are available on the AT expansion bus.
Interrupt
Sources
Used Onboard
IRQ0
ROM-BIOS clock tick function, from timer 0
Yes
IRQ1
Keyboard controller output buffer full
Yes
IRQ2
Used for cascade 2. 8259
Yes
IRQ3
COM2 serial port
Yes
IRQ4
COM1 serial port
Yes
IRQ5
LPT2 parallel printer (if present)
No
IRQ6
Floppy controller
Yes
IRQ7
LPT1 parallel printer
Yes
IRQ8
Battery backed clock
Yes
IRQ9
Free for user
No
IRQ10
Free for user
No
IRQ11
Free for user
No
IRQ12
PS/2 mouse
Yes
IRQ13
Math. coprocessor
Yes
IRQ14
Hard disk IDE / SCSI
Yes
IRQ15
Free for user
No
It may depend on the LAN configuration.
IRQ 15 = if option CF is not assembled, then free for user.
5.3.2.
Timers and Counters
5.3.2.1. Programmable Timers
An 8253 compatible timer/counter device is also included in the board's ASIC device. This device is utilized
in precisely the same manner as in a standard AT implementation. Each channel of the 8253 is driven by a
1.190MHz clock, derived from a 14.318MHz oscillator, which can be internally divided in order to provide a
variety of frequencies.
in precisely the same manner as in a standard AT implementation. Each channel of the 8253 is driven by a
1.190MHz clock, derived from a 14.318MHz oscillator, which can be internally divided in order to provide a
variety of frequencies.
Timer 2 can also be used as a general purpose timer if the speaker function is not required.
Timer Assignment
Timer
Function
0
ROM-BIOS clock tick (18.2Hz)
1
DRAM refresh request timing (15µs)
2
Speaker tone generation time base
5.3.2.2. Watchdog
The watchdog timer detects a system crash and performs a hardware reset. After power up, the watchdog is
always disabled as the BIOS does not send strobes to the watchdog. In case the user wants to take
advantage of the watchdog, the application must produce a strobe at least every 800ms. If no strobe occurs
within the 800ms, the watchdog resets the system.
always disabled as the BIOS does not send strobes to the watchdog. In case the user wants to take
advantage of the watchdog, the application must produce a strobe at least every 800ms. If no strobe occurs
within the 800ms, the watchdog resets the system.
5.3.3.
Core BIOS Download
See the separate driver/software/BIOS manual, GEODE_LX800-900.