Texas Instruments ADS61B23EVM 用户手册
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Connecting to FPGA Platforms
4.1
TSW1100
4.2
TSW1200
www.ti.com
Connecting to FPGA Platforms
The ADS61xx/ADS61B23 EVM provides several connection options to mate the EVM to various FPGA
development platforms and FPGA-based capture boards.
development platforms and FPGA-based capture boards.
Using the accompanying CMOS breakout board, users can easily mate TI's
capture board to
the ADS61xx/ADS61B23 EVM. Simply connect the breakout board to the J2 (Channel 2) connector on the
TSW1100. From an orientation standpoint, the Xilinx™ FPGA faces the ADC when correctly configured.
TSW1100. From an orientation standpoint, the Xilinx™ FPGA faces the ADC when correctly configured.
Before using the TSW1100 to capture ADC data for the first time, users should update the TSW1100
Supported_ADCs.txt file. They should explore the accompanying ADS61xx/ADS61B23 software CD and
replace the installed TSW1100 Supported_ADC.txt file with the one found on the CD; this file adds
TSW1100 support for both the ADS612x and ADS614x.
Supported_ADCs.txt file. They should explore the accompanying ADS61xx/ADS61B23 software CD and
replace the installed TSW1100 Supported_ADC.txt file with the one found on the CD; this file adds
TSW1100 support for both the ADS612x and ADS614x.
Finally, users should ensure that the ADC61xxEVM is configured in CMOS output mode. In addition, the
TSW1100 represents a load greater than 5 pF and as such, users should consider boosting the CMOS
drive strength by using the TI SPI Control software. In many cases, the boosting of the drive strength is
not required to perform valid data captures when using the TSW1100; this is an optional step.
TSW1100 represents a load greater than 5 pF and as such, users should consider boosting the CMOS
drive strength by using the TI SPI Control software. In many cases, the boosting of the drive strength is
not required to perform valid data captures when using the TSW1100; this is an optional step.
The ADS61xx/ADS61B23 natively plugs into the TSW1200 FPGA platform. In most circumstances, the
TSW1200 functions as a deserializer. However, the Virtex™-4 FPGA can be reprogrammed to allow the
ultimate in flexible solution prototyping. For users wishing to apply FPGA control over the
ADS61xx/ADS61B23 SPI interface, move the surface-mount jumpers into the following positions.
TSW1200 functions as a deserializer. However, the Virtex™-4 FPGA can be reprogrammed to allow the
ultimate in flexible solution prototyping. For users wishing to apply FPGA control over the
ADS61xx/ADS61B23 SPI interface, move the surface-mount jumpers into the following positions.
•
Move the jumper on J2 (SEN) to the 1–2 position, and remove R7 and populate R62 with a 0-
Ω
resistor.
•
Move the jumper on J7 (SCLK) to the 1–2 position, and remove R20 while installing the 0-
Ω
resistor to
R63.
•
Move the jumper on J6 (SDATA) to the 1–2 position, and remove R19 while installing the 0-
Ω
resistor
to R64.
•
Remove R18.
•
Move the jumper on J3 to position 1–2 to configure the ADC into the SPI operation mode (serial
interface mode).
interface mode).
SLAU206B – September 2007 – Revised April 2008
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