Texas Instruments TMS320DM643 用户手册
List of Tables
1
PLLC2 Configuration
2
DDR2 Memory Controller Signal Descriptions
3
DDR2 SDRAM Commands
4
Truth Table for DDR2 SDRAM Commands
5
Addressable Memory Ranges
6
16-Bit External Memory
7
32-Bit External Memory
8
Bank Configuration Register Fields for Address Mapping
9
Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM
10
Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM
11
DDR2 Memory Controller FIFO Description
12
Refresh Urgency Levels
13
Reset Sources
14
DDR2 SDRAM Configuration by MRS Command
15
DDR2 SDRAM Configuration by EMRS(1) Command
16
SDRAM Bank Configuration Register (SDBCR) Configuration
17
DDR2 Memory Refresh Specification
18
SDRAM Refresh Control Register (SDRCR) Configuration
19
SDRAM Timing Register (SDTIMR) Configuration
20
SDRAM Timing Register 2 (SDTIMR2) Configuration
21
DDR PHY Control Register (DDRPHYCR) Configuration
22
DDR2 Memory Controller Registers Relative to Base Address 2000 0000h
23
DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h
24
DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h
25
SDRAM Status Register (SDRSTAT) Field Descriptions
26
SDRAM Bank Configuration Register (SDBCR) Field Descriptions
27
SDRAM Refresh Control Register (SDRCR) Field Descriptions
28
SDRAM Timing Register (SDTIMR) Field Descriptions
29
SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
30
Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
31
Interrupt Raw Register (IRR) Field Descriptions
32
Interrupt Masked Register (IMR) Field Descriptions
33
Interrupt Mask Set Register (IMSR) Field Descriptions
34
Interrupt Mask Clear Register (IMCR) Field Descriptions
35
DDR PHY Control Register (DDRPHYCR) Field Descriptions
36
VTP IO Control Register (VTPIOCR) Field Descriptions
37
DDR VTP Register (DDRVTPR) Field Descriptions
38
DDR VTP Enable Register (DDRVTPER) Field Descriptions
A-1
Document Revision History
SPRU986B – November 2007
List of Tables
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