Lucent Technologies R5SI 用户手册
DEFINITY Enterprise Communications Server Release 5
Maintenance and Test for R5vs/si
Maintenance and Test for R5vs/si
555-230-123
Issue 1
April 1997
Maintenance Object Repair Procedures
Page 10-1190
PROCR (TN790 RISC Processor Circuit Pack)
10
Error Log Entries and Test to Clear Values
Notes:
a. The BOOTPROM Checksum Test (#80) failed. Refer to the FAIL condition
of this test for further action.
b. A parity error was detected in the processor’s data cache or instruction
cache. Aux Data indicates the difference in the number of parity errors
since the last report.
since the last report.
c. The Processor Bus Time-out Test (#82) failed. Refer to the FAIL condition
of this test for further action.
d. Aux Data of 100 is an LMM initialization failure.
e. The Processor Sanity Timer Test failed during a reset level 4 or 5
initialization. reset system 4 at the customers convenience and if the alarm
occurs again, replace the processor circuit pack. The system runs with
this failure, but it is not protected if the system software has a sanity
problem. The test processor a/b long clear command clears this alarm,
but the sanity timer is only tested during initialization so the alarm occurs
again and the system is not protected against insane software.
occurs again, replace the processor circuit pack. The system runs with
this failure, but it is not protected if the system software has a sanity
problem. The test processor a/b long clear command clears this alarm,
but the sanity timer is only tested during initialization so the alarm occurs
again and the system is not protected against insane software.
1.
The MTP Reset Test (#101) logs you off. The MTP Dual Port Ram Test (#104) can also log you off.
2.
Run the Short Test Sequence first. If all tests pass, run the Long Test Sequence. Refer to the
appropriate test description and follow the recommended procedures.
appropriate test description and follow the recommended procedures.
Table 10-366.
RISC Processor Circuit Pack Error Log Entries
Error Type
Aux
Data
Associated Test
Alarm
Level
On/Of
f Board
Test to Clear Value
1
0
2
0
Any
Any
Any
test processor a/b r 1
1(a)
Any
BOOTPROM Checksum Test
(#80)
(#80)
MAJOR
ON
test processor a/b r 5
513
Processor Write Buffer Test
(#900)
(#900)
MAJOR
ON
test processor a/b r 1
1025(b)
Any
Processor Cache Audit
(#896)
(#896)
MINOR
ON
test processor a/b r 2
1281
Any
Processor Cache Test(#895)
MAJOR
ON
test processor a/b r 1
1793(c)
Processor Bus Time-out
Exception Test (#82)
Exception Test (#82)
MAJOR
ON
test processor a/b r 2
2049(d)(e)
Any
Processor Sanity Timer Test
MINOR
ON
test processor a/b l c
2305(d)(f)
Any
Address Matcher Test
none
ON
test processor a/b l c