Lucent Technologies R5SI 用户手册
DEFINITY Enterprise Communications Server Release 5
Maintenance and Test for R5vs/si
Maintenance and Test for R5vs/si
555-230-123
Issue 1
April 1997
Packet Bus Fault Isolation and Correction
Page 9-29
Packet Bus Fault Correction
9
!
WARNING:
If this is a High or Critical Reliability system, and if the slot is in the
Active control carrier, perform an SPE interchange before changing
the circuit pack. Follow the procedures presented in
Active control carrier, perform an SPE interchange before changing
the circuit pack. Follow the procedures presented in
■
If the backplane pins are not bent, reinsert the circuit pack(s), and
perform Procedure 2 for the next set of circuit packs.
perform Procedure 2 for the next set of circuit packs.
4. If the Packet Bus fault is not present, do the following:
■
Reinsert a circuit pack. If multiple circuit packs have been
removed, reinsert the circuit packs
removed, reinsert the circuit packs
one at a time
, and repeat the
following substeps until all of the circuit packs have been
reinserted.
reinserted.
■
Determine if the Packet Bus fault has returned.
■
If the Packet Bus fault has returned, the reinserted circuit pack is
defective. Replace the circuit pack and then continue.
defective. Replace the circuit pack and then continue.
■
If the Packet Bus fault does not return when all of the circuit packs
have been reinserted, the procedure is completed.
have been reinserted, the procedure is completed.
Continue with Procedure 3 if all the port circuit packs have been checked, but
the Packet Bus fault is still not resolved.
the Packet Bus fault is still not resolved.
Procedure 3
Procedure 3 removes and reinserts control carrier circuit packs one at a time.
The Packet Control, Tone-Clock, and Expansion Interface circuit packs are the
only processor complex circuit packs that communicate on the Packet Bus. In
addition, the Memory 1 and EPN Maintenance Board circuit packs are
connected to the Packet Bus in the backplane (while the Memory 2 circuit pack is
not). Therefore, these are the only processor complex circuit packs that are likely
to cause a Packet Bus problem in a stable system. As a result, Procedure 3
should be performed only on the Packet Control, Memory 1, and EPN
Maintenance Board circuit packs in all systems, and on the Expansion Interface
and Tone-Clock circuit packs in High and Critical Reliability systems.
The Packet Control, Tone-Clock, and Expansion Interface circuit packs are the
only processor complex circuit packs that communicate on the Packet Bus. In
addition, the Memory 1 and EPN Maintenance Board circuit packs are
connected to the Packet Bus in the backplane (while the Memory 2 circuit pack is
not). Therefore, these are the only processor complex circuit packs that are likely
to cause a Packet Bus problem in a stable system. As a result, Procedure 3
should be performed only on the Packet Control, Memory 1, and EPN
Maintenance Board circuit packs in all systems, and on the Expansion Interface
and Tone-Clock circuit packs in High and Critical Reliability systems.
!
CAUTION:
If the TN771 Standalone mode does NOT indicate Packet Bus faults,
perform Procedure 3 for ONLY the Packet Control, Expansion Interface,
and Tone-Clock circuit packs. Also, problems with the backplane pins need
not be checked for. Determining if the problem is resolved by removing
circuit packs is sufficient.
perform Procedure 3 for ONLY the Packet Control, Expansion Interface,
and Tone-Clock circuit packs. Also, problems with the backplane pins need
not be checked for. Determining if the problem is resolved by removing
circuit packs is sufficient.
In a system without High or Critical Reliability
, do the following: