Renesas 16-bit single-chip microcomputer 用户手册

Rev.1.02 Jul 01, 2005 page 300 of 314
REJ09B0126-0102

M16C/6N Group (M16C/6NL, M16C/6NN)

22. Usage Precaution

Under development

This document is under development and its contents are subject to change.

Figure 22.5 When Updating Period of CAN Module Matches Access Period from CPU

fCAN

✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read

period, it does not enter reset mode, for the CPU read has the higher priority.

CPU read signal

CPU reset signal

Updating period of
CAN module

C0STR register

b8: State_Reset bit

0: CAN operation

mode

1: CAN reset/initial-

ization mode

Figure 22.6 With a Wait Time of 3fCAN Before CPU Read

Figure 22.7 When Polling Period of CPU is 3fCAN or Longer

: Updated without fail in period of 3fCAN

CPU read signal

CPU reset signal

Updating period of
the CAN module

C0STR register

b8: State_Reset bit

Wait time

0: CAN operation

mode

1: CAN reset/initial-

ization mode

CPU read signal

CPU reset signal

Updating period of
the CAN module

C0STR register

b8: State_Reset bit

CAN

0: CAN operation

mode

1: CAN reset/initial-

ization mode

: Updated without fail in period of 4fCAN

✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read

period, it does not enter reset mode, for the CPU read has the higher priority.