Freescale Semiconductor MC68HC908MR16 用户手册
Serial Peripheral Interface Module (SPI)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
208
Freescale Semiconductor
Figure 15-12. SPRF/SPTE CPU Interrupt Timing
15.10 Low-Power Mode
The WAIT instruction puts the MCU in a low power-consumption standby mode.
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). See
requests by setting the error interrupt enable bit (ERRIE). See
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit
data register in break mode does not initiate a transmission nor is this data transferred into the shift
register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
data register in break mode does not initiate a transmission nor is this data transferred into the shift
register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
15.11 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. The pins are:
•
MISO — Data received
•
MOSI — Data transmitted
•
SPSCK — Serial clock
•
SS — Slave select
BIT
3
MOSI
SPSCK
SPTE
WRITE TO SPDR
1
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
3
1
2
2
3
5
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
SPRF
READ SPSCR
MSBBIT
6
BIT
5
BIT
4
BIT
2
BIT
1
LSBMSBBIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
LSBMSBBIT
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
BYTE 3 TRANSFERS FROM TRANSMIT DATA
5
8
10
8
10
4
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
6
CPU READS SPSCR WITH SPRF BIT SET.
4
6
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
9
11
AND CLEARING SPTE BIT.
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
SPRF BIT.
3 AND CLEARING SPTE BIT.
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
SPRF BIT.
12 CPU READS SPDR, CLEARING SPRF BIT.
BIT
5
BIT
4
BYTE 1
BYTE 2
BYTE 3
7
12
READ SPDR
7
CPU READS SPDR, CLEARING SPRF BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
CPHA:CPOL = 1:0