Fujitsu FR81S 用户手册
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
116
4.5.1.
I
2
C Bus Control Register: IBCR
I
2
C bus control register (IBCR) indicates master/slave mode selection, generation of repeat start condition,
acknowledge enable, interrupt enable setting, and display of interrupt flag.
IBCRn(n=3 to 8, 10, 11) : Address Base addr + 00H (Access: Byte, Half-word,
Word)
7
6
5
4
3
2
1
0
bit
MSS ACT/SCC ACKE WSEL
CNDE
INTE
BER
INT
0
0
0
0
0
0
0
0
Initial value
R,W
R,W
R/W
R/W
R/W
R/W
R,WX R(RM1),
W
Attribute
Bit name
Function
bit7 MSS:
Master/slave
select bit
⋅
This bit selects master mode when it is set to "1" while I
2
C bus is in the idle state
(ISMK:EN="1", IBSR:BB="0")
⋅
When the BB bit in IBSR register is "1" if you set "1" to this bit, this microcontroller
waits for the start condition until the IBSR:BB bit turns to "0". While waiting, if the
slave address matches and it operates as slave, this bit will turn to "0", the AL bit in
IBSR register will turn to "1".
⋅
When master is running (MSS="1", ACT="1") and interrupt flag (INT) is "1", if you
write "0" to this bit, a stop condition occurs.
MSS bit will be cleared on the following conditions.
(1) I
2
C interface disable (ISMK:EN bit="0")
(2) When arbitration lost occurred
(3) Bus error detected (BER bit="1")
(4) Write "0" to the MSS bit when INT = "1"
(5) The DMA mode is enabled (SSR:DMA=1) and "0" writing in the MSS bit at SSR:TBI
="1".
The relation between MSS bit and ACT bit is as follows.
MSS=0, ACT=0 idle
MSS=0, ACT=1 slave address matches or responds ACK * to the reserved address and the
slave is in operation (slave mode)
MSS=1, ACT=0 master operation wait
MSS=1, ACT=1 master is in operation (master mode)
*: ACK response: indicates that SDA of I
2
C bus is "L" in the acknowledge interval.
Notes:
⋅
If the DMA mode is prohibited (SSR:DMA=0) and the MSS bit is set to "1", the MSS bit
can be changed to "0" when MSS bit ="1" and INT bit ="1". When "0" is written in the
MSS bit when the ACT bit is "1", the INT bit is cleared to "0".
⋅
If the DMA mode is permitted (SSR:DMA=1) and the MSS bit is set to "1", the MSS bit
can be changed to "0" when MSS bit ="1", INT bit ="1" or the SSR:TBI bit is "1".
When "0" is written in the MSS bit when the ACT bit is "1", the INT bit is cleared to "0".
⋅
While the master is in operation, even if you write "0" to the MSS bit, "1" will still be
read out while the ACT bit stays "1".
MB91520 Series
MN705-00010-1v0-E
1429