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CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
5. Operation of UART
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
151
5.2.2.
Transmission Operation
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If the transmission data empty flag bit (TDRE) of the serial status register (SSR) is "1", the transmission
data can be written to the transmit data register (TDR). (If the transmission FIFO is enabled, transmission
data can be written even if TDRE="0").
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When transmission data is written to the transmit data register (TDR), the transmission data empty flag
bit (TDRE) becomes "0".
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When the transmission operation enable bit of the serial control register (SCR:TXE) is set to "1", the
transmission data is loaded into the transmit shift register and the transmission starts from the start bit
sequentially.
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When the transmission starts the transmission data empty flag bit (SSR:TDRE) will be set to "1" again. If
the transmission interrupt is enabled (SCR:TIE=1) at this time, a transmission interrupt occurs.
Following transmission data can be written to the transmit data register when processing interrupts.
Notes:
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As soon as the transmission interrupt is enabled (SCR:TIE), a transmission interrupt occurs, because the
transmission data empty flag bit (SSR:TDRE) has the initial value "1".
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As soon as the FIFO transmission interrupt is enabled (FCR1:FTIE=1), a transmission interrupt will
occur, because the FIFO transmission data request bit (FCR1:FDRQ) has the initial value "1".
MB91520 Series
MN705-00010-1v0-E
1464