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CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
5. Operation of UART
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
159
5.2.10.
Hardware Flow Control
When the flow control is enabled (ESCR:FLWEN="1"), UART controls the hardware flow.
⋅
At data transmission
When CTS is "H" after data transmission, it will not transmit the next data and wait for the transmission
until the CTS turns to "L" even when the transmission buffer contains data (TDRE="0"). If it waits for
the transmission, input "H" to CTS before the stop bit transmission is completed. Transmission will
continue until the stop is reached even if "H" is input to CTS during the transmission.
Figure 5-10 Hardware Flow Control Operation at Data Transmission
(SMR:SBL="0", ESCR:ESBL=INV=PEN=L2=L1=L0="0")
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
Transmission data
TDRE
Write to TDR
During
transmission
WAIT
CTS
⋅
At data reception
⋅
In case of FIFO unused
It outputs "H" to RTS when the data on the one bit prior to the stop bit is received. It outputs "L" to
RTS
after the reception data is read.
Figure 5-11 Hardware Flow Control Operation at Data Reception (FIFO not used)
(SMR:SBL="0", ESCR:ESBL=INV=PEN=L2=L1=L0="0")
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
Reception data
RDRF
Reading from RDR
RTS
MB91520 Series
MN705-00010-1v0-E
1472