Fujitsu FR81S 用户手册
CHAPTER 45: FLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : FLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
Figure 5-2 Example of Write Procedure
NO
YES
0
1
Start of writing
Set the FWE bit of FLASH control
register (FCTLR) to enable writing
to flash (FWE = 1).
Write command sequence
Addr: x554 Data: 00AA
Addr: yAA8 Data: 0055
Addr: x554 Data: 00A0
Addr: Address Data: Data
Internal address reading out
Next address
Data
Reading out (dummy)
*
Data polling
(DPOLL bit)
Inverted data
Timing limit
(TLOV bit)
Data
Write error
Last address
Set the FWE bit of FLASH control
register (FCTLR) to disable writing
to flash (FWE = 0).
End of writing
: Verify with a hardware sequence flag.
*: When reading out the FSTR
register instead of reading
out the hardware sequence
flag, ignore the first read
value (it is unnecessary to
read out the dummy when
reading out the hardware
sequence flag).
MB91520 Series
MN705-00010-1v0-E
1960