Fujitsu FR81S 用户手册
CHAPTER 16: INTERRUPT REQUEST BATCH READ
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : INTERRUPT REQUEST BATCH READ
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
4.10. Interrupt Request Batch Read Register 5 lower-order :
IRPR5L (Interrupt Request Peripheral Read register
5L)
5L)
The bit configuration of the interrupt request batch read register 5 lower-order is explained.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #36)
IRPR5L : Address 0423
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CANIR2
UDCIR0
UDCIR1
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute
R,WX
R,WX
R,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
[bit7] CANIR2 (CAN Interrupt Request 2) : CAN ch.2 Interrupt Request
[bit6] UDCIR0 ( UpDown Counter Interrupt Request 0 ) : Up/Down counter ch.0 Interrupt Request
[bit5] UDCIR1 ( UpDown Counter Interrupt Request 1 ) : Up/Down counter ch.1 Interrupt Request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
MB91520 Series
MN705-00010-1v0-E
520