Fujitsu FR81S 用户手册
CHAPTER 16: INTERRUPT REQUEST BATCH READ
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : INTERRUPT REQUEST BATCH READ
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
4.29. Interrupt Request Batch Read Register 15
upper-order : IRPR15H (Interrupt Request Peripheral
Read register 15H)
Read register 15H)
The bit configuration of the interrupt request batch read register 15 upper-order is explained.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #15)
IRPR15H : Address 0436
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EXTNMI XB_ECC_DE BR_ECC_DE
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R,WX
R,WX
R,WX
R0,WX R0,WX R0,WX R0,WX
R0,WX
[bit7] EXTNMI : External NMI Request
The EXTNMI bit is set by detecting external NMI request, and cleared by reading this register.
[bit6] XB_ECC_DE : XBS RAM double bit error generation Interrupt Request
[bit5] BR_ECC_DE : Backup RAM double bit error generation Interrupt Request
[bit5] BR_ECC_DE : Backup RAM double bit error generation Interrupt Request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
Set
EXTNMI bit
Clear
External NMI request
detection
IRPR15H
read or reset
MB91520 Series
MN705-00010-1v0-E
539