Fujitsu FR81S 用户手册
CHAPTER 18: WATCHDOG TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WATCHDOG TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
5.1.3. Operation
This section explains operation of the software watchdog function.
The operation of the watchdog timer 0 after activation is explained
Counting Conditions
The watchdog timer 0 counts the rising edges of the peripheral clock (PCLK) while the CPU is operating.
DMA transfer does not influence the watchdog timer 0 to count.
As in sleep mode, the watchdog timer 0 stops counting only while the CPU is being stopped. Since
Counting Conditions
The watchdog timer 0 counts the rising edges of the peripheral clock (PCLK) while the CPU is operating.
DMA transfer does not influence the watchdog timer 0 to count.
As in sleep mode, the watchdog timer 0 stops counting only while the CPU is being stopped. Since
sampling of operating state of the CPU is done by the peripheral clock, a change in the operating state of the
CPU occurring within the period of the peripheral clock is ignored.
When the watchdog timer 0 is connected with ICE, the timer stops counting under the following conditions:
-In emulator mode
-In the debug interface functions, if the watchdog reset suppression function is enabled.
Under any conditions mentioned above, when the watchdog timer 0 stops counting it pauses without
When the watchdog timer 0 is connected with ICE, the timer stops counting under the following conditions:
-In emulator mode
-In the debug interface functions, if the watchdog reset suppression function is enabled.
Under any conditions mentioned above, when the watchdog timer 0 stops counting it pauses without
clearing the counter. Hence, when the watchdog timer 0 resumes counting the timer will continue counting
from the previous count.
Because the peripheral clock stops during the oscillation stabilization wait time of the source clock, the
watchdog timer 0 also stops counting.
Clearing the Timer
Once the watchdog timer 0 is activated, the timer must be cleared before the timer period has elapses.
Clearing the watchdog timer 0 is performed by writing data to the register WDTCPR0. These data written
must be the inverted values of all bits of the WDTCPR0 that was written previously.
When the watchdog timer 0 is activated with the set value "0x55", for example, written to the register
WDTCPR0, the timer is cleared in the following way:
- After activation of the watchdog timer 0, the set value should be written alternately like "0xAA" then
"0x55" then "0xAA" then "0x55".
Since the read value of the register WDTCPR0 is always "0x00", the previously written value cannot be
determined by reading WDTCPR0. For this reason, if the previously written value cannot be stored in other
location, write to the register two times consecutively in a single clear.
When the window function is effective during the watching period, clear the timer within a period of time
while the counter can be cleared effectively.
Reset Request Generation
The watchdog timer 0 generates a watchdog rest request under the following conditions:
⋅
⋅
An overflow of the configured watchdog timer cycle occurs.
⋅
There is a transition to watch mode or to stop mode while stop mode detection reset is enabled.
⋅
A value, other than the inverted value of the value which is previously written, is written to the clear
register.
⋅
Writing to the clear register within the lower limit of the watching period of the window function.
MB91520 Series
MN705-00010-1v0-E
629