Fujitsu FR81S 用户手册
CHAPTER 19: BASE TIMER
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
3. Configuration
This section explains the configuration of the base timer.
Figure 3-1 Block Diagram (Overview)
Counter
Trigger logic
Interrupt logic
Registers
Counter
Trigger logic
Interrupt logic
Registers
I/O selection
register
register
(BTSEL01)
I/O selection logic
Interrupt
IRQ0 : Underflow/overflow/duty match
IRQ1 : Trigger/measurement completion interrupt
IRQ0 : Underflow/overflow/duty match
IRQ1 : Trigger/measurement completion interrupt
Interrupt
IRQ0, IRQ1
Bus access
Channel 0
Channel 1
Interrupt
IRQ0, IRQ1
TIOA0
TIOA1
(Input for I/O mode1 and output or
unused for other than I/O mode 1)
TIOB0 TIOB1
Simultaneous
software activation
register (BTSSSR)
Base Timer
MB91520 Series
MN705-00010-1v0-E
642