Fujitsu FR81S 用户手册
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
74
Notes:
⋅
The output method and output destination of the output signal (TOUT) from the 16-bit PPG timer
depend on the following settings:
⋅
Base timer I/O mode
⋅
TIOA0, TIOA1 pin functions
⋅
If the count timing of the 16-bit down counter and the load timing occur at the same time, the load
operation is given precedence.
Write Timing
The values of the base timer x L width setting reload register (BTxPRLL) and base timer x H width setting
reload register (BTxPRLH) are reloaded at the following timing:
The value set in the base timer x L width setting reload register (BTxPRLL)
It is loaded to the 16-bit down counter in one of the following events:
⋅
An activation trigger is detected.
⋅
An underflow occurs after counting down from the value of the base timer x H width setting reload
register (BTxPRLH) is completed.
The value set in the base timer x H width setting reload register (BTxPRLH)
It is transferred to the buffer in one of the following events:
⋅
An activation trigger is detected.
⋅
An underflow occurs after counting down from the value of the base timer x H width setting reload
register (BTxPRLH) is completed.
The content of the buffer is loaded to the 16-bit down counter in the following event:
⋅
Counting down from the value of the base timer x L width setting reload register (BTxPRLL) is
completed.
Therefore, rewrite the base timer x L width setting reload register (BTxPRLL) and base timer x H width
setting reload register (BTxPRLH) during the period from the time an underflow occurs (the UDIR bit of the
status control register (BTxSTC) changes to "1") to the time counting based on the next cycle begins. The new
data will be effective as the next cycle.
MB91520 Series
MN705-00010-1v0-E
707