Fujitsu FR81S 用户手册
CHAPTER 20: RELOAD TIMER
6. Application Note
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
62
* 1: TIN effective level setting
TRGM[1:0]= x0------Count only for TIN=L input interval
TRGM[1:0]= x1------Count only for TIN=H input interval
* 2:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
* 3:TOUT output polarity setting
OUTL= 0------
Initial value L=> Count L from TMRLRA => H when an underflow occurs =>
Count H from TMRLRB => L when an underflow occurs
OUTL= 1------
Initial value H=> Count H from TMRLRA => L when an underflow occurs =>
Count L from TMRLRB => H when an underflow occurs
*4:Reload setting when an underflow occurs
RELD=0------One-shot mode
RELD=1------Reload mode
*5:Interrupt request enable setting
INTE=0------Interrupt disabled
INTE=1------Interrupt enabled
MB91520 Series
MN705-00010-1v0-E
789