Fujitsu FR81S 用户手册
CHAPTER 23: 32-BIT INPUT CAPTURE
7. Q&A
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CHAPTER
: 32-BIT INPUT CAPTURE
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7.3. About Interrupt Related Registers
This section shows interrupt related registers.
Input capture interrupt vector and input capture interrupt level settings
See "Table of Interrupt Vector" in "APPENDIX" for interrupt number.
The interrupt level is set by the ICR register. For details of the interrupt levels, see "CHAPTER: INTERRUPT
CONTROL (INTERRUPT CONTROLLER)".
Interrupt request flags ((ICS45.ICP4), (ICS45.ICP5), (ICS67.ICP6), (ICS67.ICP7), (ICS89.ICP8),
(ICS89.ICP9)) are not cleared automatically. Therefore, clear the input capture interrupt request flags by
writing "0" using software before returning from interrupt processing.
MB91520 Series
MN705-00010-1v0-E
902