Analog Devices ADSP-21535 E-KIT LITE 用户手册
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4.2.1 External Bus Interface
The External Bus Interface Unit (EBIU) is connected to 4M x 32 bits of SDRAM
(16 MB). This memory is connected to the synchronous memory select 0
(~SMS0) pin. Refer to section
(16 MB). This memory is connected to the synchronous memory select 0
(~SMS0) pin. Refer to section
for information about configuring the
SDRAM.
The EBIU is also connected to 272K x 16 bits of flash memory. This memory is
connected to the asynchronous memory select (~AMS0) pin. The DSP can use
this memory both for booting and storing information during normal operation.
Refer to section
connected to the asynchronous memory select (~AMS0) pin. The DSP can use
this memory both for booting and storing information during normal operation.
Refer to section
for information about using the flash memory.
All of the address, data, and control signals are available externally via the
extender connectors (P1-3). The pinout of these connectors can be found in
extender connectors (P1-3). The pinout of these connectors can be found in
4.2.2 SPORT0 – Audio Interface
SPORT0). is connected to the AD1885 SoundMAX Codec (U7). Two 3.5mm
stereo jacks (P5, P6) allow audio to be input and output. You can supply an audio
input to the Codec microphone input channel (MIC1) or to the stereo LINE_IN
input channel. The jumper settings of JP1 determine the Codec channel driven by
the input jack (P5). For information about configuring JP1, see section
stereo jacks (P5, P6) allow audio to be input and output. You can supply an audio
input to the Codec microphone input channel (MIC1) or to the stereo LINE_IN
input channel. The jumper settings of JP1 determine the Codec channel driven by
the input jack (P5). For information about configuring JP1, see section
SPORT0 is also routed to an off-board connector (P9). When using the off-board
connector, the Codec must be held in reset, so that it does not drive any of the
SPORT0 signals. The Codec can be held in reset by driving PF15 low or by
setting up JP2 to always hold the Codec in reset (see section
connector, the Codec must be held in reset, so that it does not drive any of the
SPORT0 signals. The Codec can be held in reset by driving PF15 low or by
setting up JP2 to always hold the Codec in reset (see section
). PF15 must be
pulled HI (1) for the Codec to function.
! NOTE: TCLK0 and RCLK0 pins are shorted together using R114 and
R118.
ADSP-21535 EZ-KIT Lite Evaluation System Manual
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