M-Systems Flash Disk Pioneers Flash Memory 用户手册

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Implementing MLC NAND Flash for Cost-Effective, High-Capacity Memory 
91-SR-014-02-8L 
Table 1 maps the various features of x2 technology against the three major areas of MLC limitations 
that they overcome. The remainder of this section explains how each feature achieves these 
enhancements in Mobile DiskOnChip G3. 
Table 1: Overcoming MLC Limitations with x2-based Mobile DiskOnChip G3  
Areas of MLC Enhancement  
x2 Technology Feature 
Reliability Performance 
Flash 
Management 
TrueFFS 
Robust flash management 
Enhanced EDC 
Enhanced ECC 
Efficient bad block 
handling 
 
Thin Controller 
MultiBurst  
 
 
DMA support 
 
a
 
 
Parallel multiplane access 
 
a
 
 
Flash Media 
Two parallel planes 
 
a
 
a
 
Robust Flash Management 
To overcome MLC flash access and partial programming limitations that affect all three areas of 
MLC limitations, x2 technology uses a specially customized translation layer called Sequential 
Access Flash Translation Layer (SAFTL). SAFTL is incorporated seamlessly into M-Systems’ 
TrueFFS. It maps each virtual unit into a chain of physical units, much in the same way that 
translation layers for Binary flash operate. However, unlike traditional translation layers, SAFTL 
does not implement one-to-one simple mapping between the virtual sector offset in the virtual unit 
and its physical location in the physical units. Instead, the data of a virtual sector can be in any 
location within the physical unit chain of its virtual unit. Each physical sector containing data also 
contains the offset of its corresponding virtual sector in its virtual unit. 
SAFTL enables each physical unit to be filled sequentially, as required by MLC flash, starting from 
the first sector to the last. Each write request to the corresponding virtual unit is written to the next 
free physical sector, regardless of the virtual sector number requested to be written. When a physical 
unit is full and a new write request arrives, a new free physical unit is allocated and added to the 
chain. New unit allocation always occurs concurrently with writing a sector, so that sector data and 
unit control data can be written in one operation to improve performance.